Tải bản đầy đủ

Phát triển giao tiếp usb sử dụng vi điều khiển

ABSTRACT
USB (Universal Serial Bus) interface has many applications in computer
communication because it can transfer the data in high speed. The aim for this work
has been to develop a USB interface that it can transfer data to and from FPGA and
computer via an EZ-USB FX2PL microcontroller from Cypress semiconductor. The
work is intended to be used in nuclear instrumentation development at Nuclear
Physics Department, Faculty of Physics and Engineering Physics, University of
Science HCMC. The development is designed to be used to replace the RS-232
interface in some nuclear electronic devices which have the connection with
computer in order to increase the transfer rate. An EXK board is used as a
reference hardware that includes an FPGA Spartan-3E from Xilinx and an EZ-USB
FX2LP microcontroller. The microcontroller was chosen because it is a high-speed
USB microcontroller. We develop the firmware for Cypress chip by C-language and
using VHDL to implement for FPGA. To show the data on the screen, a user
interface is developed by visual C#. The thesis is arranged with 4 chapters:
Chapter 1: Introduce the purpose and the main components of this work.
Chapter 2: Introduce the hardware design.
Chapter 3: Introduce the software design.
Chapter 4: Results and Discussion.
The conclusion gives summary of results.
In future work section, some proposals to improve the system are suggested.

This section also discusses its applications for the near future.
In appendix A, you can find some VHDL codes for FPGA Xilinx. Appendix B
provides firmware used to control the Cypress Chip.

i


By student, Academic year 2006-2010
Nguyen Vo Bao Ngan
(E-mail address: bao2005ngan@yahoo.com)

ii


Tóm tắt
PHÁT TRIỂN GIAO TIẾP USB SỬ DỤNG VI ĐIỀU KHIỂN
CYPRESS EZ-USB FX2LP VÀ CÔNG NGHỆ FPGA
Nguyễn Võ Bảo Ngân MSSV: 0613068
bao2005ngan@yahoo.com
Sinh viên khóa 2006-2010
Bộ môn Vật lý và Điện tử, Khoa Vật lý và Vật lý Kỹ thuật
Trường Đại học Khoa học Tự Nhiên, ĐHQG Tp.Hồ Chí Minh
Tiến sĩ Võ Hồng Hải
Bộ môn vật lý hạt nhân
vhhai@phys.hcmuns.edu.vn

Ngày nay USB trở nên rất phổ biến, chúng xuất hiện trên hầu hết các thiết bị điện tử
như chuột, bàn phím, máy in, điện thoại…USB có khả năng truyền dữ liệu ở tốc độ
cao và kết nối các thiết bị với máy tính mà không phải khởi động máy tính lại.
Chính vì những ưu điểm của USB, chúng tôi phát giao tiếp USB để thay thế cho
chuẩn RS-232 trên thiết bị đo lường tại bộ môn vật lý hạt nhân nói riêng và cho các
thiết bị cần truyền dữ liệu tốc độ cao.
Đề tại được thực hiện với phần cứng được thiết kế bởi một nhóm cựu sinh viên Học
Viện Kỹ Thuật Quân Sự Hà Nội. Phần cứng cho phép truyền dữ liệu giữa máy tính
và FPGA Xilinx Spartan-3E thông qua chip USB Cypress Cy7C68013A. Dòng
Cypress chip này hỗ trợ truyền ở cả 2 chế độ là ‘full speed’ và ‘high speed’.Để phần
cứng hoạt động chúng tôi viết firmware để cấu hình chip Cypress và lập trình phần
cứng cho FPGA Xilinx bằng ngôn ngữ VHDL. Đồng thời tạo giao diện để hiện thị
kết quả lên máy tính bằng Visual C#.
Kết quả mạch có thể hoạt động ổn định ở chế độ ‘full speed’, truyền dữ liệu ổn định
từ FPGA lên máy tính và hiến thị lên giao diện đã tạo ra.
Từ kết quả đạt được chúng tối sẽ tiếp tục phát
triền phần cứng cũng như phần mềm để mạch
có thể hoạt động ở chế độ ‘high speed” nhầm
nâng cao tốc độ truyền dữ liệu. Sau đó, chúng
tôi sẽ sử dụng chip Cypress để thiết kế giao tiếp
USB trên thiết bị thu nhận dữ liệu FlashADCFPGA ( được phát triển cho nghiên cứu hạt
nhân bởi đại học Osaka Nhật Bản).
iii


ACKNOWLEDGMENTS

This thesis would not have been possible without the help of a number of
people, and I would like to express my gratitude to all of them.
Professor NOMACHI MASAHARU of Osaka University helped me with
FPGA development kits.
Dr. VO HONG HAI of Department of nuclear physics helps me a lot during
doing this thesis at nuclear physics Lab.
Thanks to Dr. NGUYEN VAN HIEU and all other teachers for your help
during the study at University of Science.
Thanks to my friends and my family for your advices during writing the
thesis.
HoChiMinh City, July / 2010
Nguyen Vo Bao Ngan

iv


Comments by Supervisor

Ho Chi Minh City, July 2010.

Dr. Vo Hong Hai

v


Comment by Reviser

Ho Chi Minh City, July 2010.

BSc. Truong Thien Dinh

vi


Table of contents
Abstract…….………………………………………………………………………...i
Tóm tắt.......................................................................................................................iii
Acknowledgements..................................................................................................iv
Comments by supervisor...........................................................................................v
Comment by reviser................................................................................................vi
Table of contents.....................................................................................................vii
List of abbreviation...................................................................................................ix
List of figure..............................................................................................................x
List of table.............................................................................................................xii
CHAPTER I INTRODUCTION........................................................................1
I.1 Purpose ..................................................................................................1
I.2 USB ( Universal Serial Bus) ..................................................................1
I.3 FPGA......................................................................................................2
I.4 The main components .............................................................................2
CHAPTER II HARDWARE ...............................................................................4
II.1 Cypress EZ-USB FX2LP Microcontroller (CY7C68013A)...................6
II.2 Xilinx Spartan-3E ...............................................................................10
III.3 Large EEPROM ATMEL 24C64A......................................................12
CHAPTER III SOFTWARE .............................................................................13
III.1 Development Environment.................................................................13
III.2 Firmware ............................................................................................13
III.2.1 Firmware for Cypress............................................................13
III.2.2 Firmware for FPGA..............................................................17
III.3 EEPROM image ...............................................................................20
III.4 Drivers ..............................................................................................21
III.5 User interface......................................................................................22
CHAPTER IV RESULTS AND DISCUSSION.................................................24
Conclusion ...........................................................................................................25
Future work...........................................................................................................26
References ...........................................................................................................27
Appendix A VHDL CODE..................................................................................28
Appendix B Firmware for Cypress......................................................................37

vii


List of Abbreviations
USB

Universal Serial Bus

MCU

Micro Controller Unit

viii


CPU

Complex Programmable Logic Device

FIFO

First In First Out

VHDL

Very high speed integrated circuit Hardware Description Language

EEPROM

Electrically Erasable Programmable Read Only Memory

FPGA

Field Programmable Gate Arrays

PCB

Printed Circuit Board

VID

Vendor ID

PID

Product ID

DID

Device ID

(queue)

LIST OF FIGURES
Figure 1.1 Computer and EXF board connection ...................................................2
Figure 2.1 EXK board ............................................................................................4
Figure 2.2 Cypress module......................................................................................5
Figure 2.3 FPGA module.........................................................................................5
ix


Figure 2.4 Cypress CY7C68013A...........................................................................6
Figure 2.5 EZ-USB Endpoint buffer........................................................................7
Figure 2.6 EZ-USB FX2LP architecture..................................................................8
Figure 2.7 Connection between EZ-USB and FPGA Xilinx....................................8
Figure 2.8 Simplified example of a general FPGA logic architecture....................12
Figure 2.9 EEPROM ATMEL................................................................................12
Figure 3.1 Firmware project..................................................................................17
Figure 3.2 Interface Pins Example: Asynchronous FIFO Writes...........................18
Figure 3.3 Asynchronous FIFO Writes State Machine..........................................19
Figure 3.4 Interface Pins Example: Asynchronous FIFO Reads............................19
Figure 3.5 Asynchronous FIFO Reads State Machine...........................................20
Figure 3.6 hex2bix command................................................................................21
Figure 3.7 Windriver interface...............................................................................22
Figure 3.8 User interface using Visual Studio .Net...............................................23
Figure 4.1: Receiving data from FPGA.................................................................24

x


LIST OF TABLES
FIFO Address

xi


CHAPTER I

INTRODUCTION
Nowadays, USB interface become very popular in computer communication. It can
connect computer peripherals such as mice, keyboards, digital cameras, printers,
personal media players, flash drivers, and external hard drivers. For many of those
devices, USB has become the standard connection method. USB was designed for
personal computers, but it has become commonplace on other devices such as smart
phones, PDAs, and video game consoles, and as a power cord between a device and
an AC adapter plugged into a wall plug for charging. Because USB have many
applications in computer communication, in this work we develop an usb interface
using [1] EZ-USB FX2LP Microcontroller.
I.1 Purpose:
The purpose of this project is to develop a USB interface that employs a
microcontroller (MCU) to communicate between computer and FPGA. This would
make it possible to apply for some projects that you want to transfers data in high
speed after processing signal by FPGA.
I.2 USB
[2] USB (Universal Serial Bus): is a set of connectivity specifications developed
by Intel in collaboration with industry leaders. USB allows high-speed, easy
connection of peripherals to a PC. When plugged in, everything configures
automatically. USB is the most successful interconnect in the history of personal
computing and has migrated into consumer electronics (CE) and mobile products.
Providing an industry standard, USB was originally released in 1995 at 12 Mbps.
Today, USB operates at 480 Mbps and is found in over six billion PC, consumer

1


electronics (CE), and mobile devices with a run rate of 2 billion USB products
being shipped into the growing market every year. In addition to high performance
and ubiquity, USB enjoys strong consumer brand recognition and a reputation for
ease-of-use.
I.3 FPGA
[3] A field-programmable gate array (FPGA) is an integrated circuit designed to
be configured by the customer or designer after manufacturing - hence "fieldprogrammable". The FPGA configuration is generally specified using a hardware
description language (HDL), similar to that used for an application-specific
integrated circuit (ASIC) (circuit diagrams were previously used to specify the
configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be
used to implement any logical function that an ASIC could perform. The ability to
update the functionality after shipping, partial re-configuration of the portion of the
design and the low non-recurring engineering costs relative to an ASIC design (not
withstanding the generally higher unit cost), offer advantages for many applications.
I.4 The main components

Figure 1.1 Computer and EXF board connection

2


In this system, [4] EXF board consist of two main component: [1] Cypress
CY7C8013A and [5] Xilinx Spartan-3E. The Cypress CY7C68013A which belongs
the Cypress Semiconductor EZ-USB® family, offers with architecture designed to
accommodate the higher data rates.

The [1] EZ-USB FX2LP device

(CY7C68013A/14A/15A/16A) supports both full-speed (12Mbps) and high-speed
(480Mbps) modes.This chip will help automatically handling of most of the USB
protocol, which simplifies code and accelerates the USB learning curve. The
firmware for this Cypress chip is written by C and assembly language using Keil C
software. Cypress Console which is a software form Cypress semiconductor is used
to download the firmware to Cypress chip. There are 26 pins connected from FPGA
Xilinx to Cypress chip: data bus, control signal. A firmware for FPGA Xilinx was
written to receive the data from Cypress chip and transfer data to FIFO buffer. ISE
11.0 was used to synthesis and program to FPGA. The final problem is how to
connect to the computer. Windriver was used to create the driver for this device. In
other view the data to and from FPGA Xilinx an application connected to the driver
was needed. There are a lot of ways of creating an application that gathers the data.
One way to do it is to use Cypress C++ API CyAPI. The CyAPI.lib provides a C++
programming interface to USB devices.

3


CHAPTER II

HARDWARE

An [4] EXK board where the [1] Cypress CY7C68013A and [5] Xilinx Spartan-3E
were included was used as a reference during hardware design in this project. The
[4] EXK board independently consist of two part: Cypress board and Xilinx board.
One more material to support for this project is [6] CY3684 EZ-USB FX2LP
Development Kit from Cypress semiconductor.

Figure 2.1 EXK board

4


Figure 2.2 Cypress module

Figure 2.3 FPGA module

5


II.1 Cypress EZ-USB FX2LP Microcontroller (CY7C68013A)

Figure 2.4 Cypress CY7C68013A [7]
The microcontroller, also known as the MCU, is the part of the system that takes
care of all data transfer between computer and FPGA. The controller is a 100-pin
[1] EZ-USB FX2LP chip from Cypress semiconductor that employs an enhanced
8051 microprocessor in its core. It has an integrated USB 2.0 transceiver and
utilizes smart Serial Interface Engine (SIE) which makes it easy to communicate
over the USB. It has 16kB of program and data RAM and is running at 48Mhz.
Further it has four large, up to 4kB, endpoint FIFOs which are used
when interfacing to the USB. An endpoint is simply a communication node. A
device usually have several of these. All USB devices have at least one control
endpoint (endpoint 0) that takes care of enumeration, i.e. connecting to the host, and
similar tasks. In excess to this, devices usually have at least one endpoint for data
transfer. A host application can than connect to that specific endpoint to transfer

6


data. The data transfer endpoints on the [1] EZ-USB FX2LP are each connected to a
FIFO, thus they are called “endpoint FIFOs”. This offers the developer a buffer
when interfacing to the USB. This particular microcontroller has two control
endpoints and between one and four data transfer endpoints depending on
configuration. The different configurations for the endpoint FIFOs can be seen in
fig. 2.5. In this project two endpoints are used and they are configured to 64bytes.
The data transfer endpoints can be programmed to perform three different kinds of
transfers. BULK, INTERRUPT and ISOCHRONOUS. In this design BULK
transfers are used. This because BULK transfers can transfer data at the highest rate.
This particular MCU was chosen mainly because it is developed for
easy USB access and because it includes a SLAVE FIFO MODE. The
programmable interface enables the developer to implement a communication
between FPGA and CYPRESS. In this case, FPGA is an external master to Cypress
CY7C68013A.

Figure 2.5 EZ-USB Endpoint buffer [8]

7


Figure 2.6 EZ-USB FX2LP architecture [9]
Below is the figure 2.2 show the connection between Cypress Cy7C68013A and
FPGA Xilinx.

Figure 2.7 Connection between EZ-USB and FPGA Xilinx [10]

8


Follow is the function of every connected pins:
Slave Output Enable and Slave Read — SLOE and SLRD: In
asynchronous mode (IFCONFIG.3 = 1), the FIFO pointer is incremented on each
asserted-to-deasserted transition of SLRD. The SLOE pin enables the FD outputs.
In synchronous mode, when SLOE is asserted, this causes the FD bus to be driven
with the data that the FIFO pointer is currently pointing to. The data is pre-fetched
and is output only when SLOE is asserted. In asynchronous mode, the data is not
pre-fetched, and SLRD must be asserted when SLOE is asserted for the FD bus to
be driven with the data that the FIFO pointer is currently pointing to. SLOE has no
other function besides enabling the FD bus to be in a driven state. By default, SLOE
and SLRD are active-low; their polarities can be changed via the FIFOPINPOLAR
register.
Slave Write — SLWR In synchronous mode (IFCONFIG.3 = 0), data on the
FD bus is written to the FIFO (and the FIFO pointer is incremented) on each rising
edge of IFCLK while SLWR is asserted. In asynchronous mode (IFCONFIG.3 = 1),
data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on
each asserted-to-deasserted transition of SLWR. By default, SLWR is active-low; its
polarity can be changed via the FIFOPINPOLAR register.
FIFOADR[1:0]: The FIFOADR[1:0] pins select which of the four FIFOs is
connected to the FD bus (and, if the FIFO flags are operating in Indexed mode, they
select which FIFO’s flags are presented on the FLAGx pins):

PKTEND An external master asserts the PKTEND pin to commit an IN
packet to USB regardless of the packet’s length. PKTEND is usually used when the

9


master wishes to send a ‘short’ packet (for example, a packet smaller than the size
specified in the EPxAUTOINLENH:L registers). However, in this project
PKTEND was not used.
FD ( FIFO DATA): External logic accesses the FIFOs through an 8- or 16bit wide data bus, FD. The data bus is bidirectional, with its output driv-ers
controlled by the SLOE pin. The width is selected via each FIFO’s WORDWIDE
bit, (EPxFIFOCFG.0). It will be discussed in the firmware for Cypress.
FIFO Flag Pins (FLAGA, FLAGB, FLAGC, FLAGD) Four pins —
FLAGA, FLAGB, FLAGC, and FLAGD report the status of the EZ-USB’s FIFOs;
in addition to the usual ‘FIFO full’ and ‘FIFO empty’ signals, there is also a signal
which indicates that a FIFO has filled to a user-program-mable level.

II.2 Xilinx Spartan-3E
The main implementation target device is FPGAs, Field Programmable Gate
Arrays. The FPGA is a chip that is configurable to behave in almost any way the
user want it.
There are two main competing FPGA vendors, Altera and Xilinx, with some FPGA
families and generations each. There are other vendors as well, but this work will
only cover Xilinx.
The FPGA is normally used for digital signal processing, “glue logic”, and
other types of digital tasks. Therefore it is both generalized and specialized in the
same time. Typical FPGA components are
Logic: FPGAs are mainly built up by many small LUTs (look-up tables), FAs
(Full Adders), and DFFs (D-flipflops),
and small muxes. Many LUTs can also work as memories. Xilinx group the logic
into slices/CLBs,
Altera group it into LE/ALM/LABs. See figure 3.1 for a very simplified example of
how the structure

10


can be organized. A LUT with e.g. 6 inputs (6-LUT) can implement any
combinatorial function of those
inputs.
Memories: There use to be synchronous memory blocks, often configurable
as RAM, ROM, shift register or
FIFO buffer, and in several different heights and widths. For example the size 4
kBits = 212 bits can be
shaped as 8 bits wide and 512=29 rows high, or 32 bits wide and 128=27 rows high.
The address widths
are 9 and 7 bits in those cases, respectively.
Memories can have single port (SP) or dual port (DP) features, meaning you can
access the memory
content from one and two sides, respectively. This thesis will only use ROMs with
SP configurations, and
hence the rest of the memory configurations are not listed here. For futher
improvements the DP may be
interesting, as noted below.
In most cases there are optional bits reserved for parities, usually 1 parity bit for
each byte.
The LUTs are very small ROMs. Many of the LABs/CLBs can configure the LUTs
as e.g. RAM, but in
this thesis that is extraneous. The ROM function is implicit, and omitted in the
ROM list.
Multipliers: Most FPGAs are equipped with dedicated binary multipliers. Altera
uses 18 × 18 bits signed or
unsigned, Xilinx uses 25 × 18 signed in their latest FPGAs.
FPGAs typically contains a lots of other features as well, but nothing interesting in
this thesis.

11


Figure 2.8 Simplified example of a general FPGA logic architecture
II.3 Large EEPROM ATMEL 24C64A

Figure 2.9 EEPROM ATMEL [11]
Since the MCU only has volatile programmable on-chip memory the system need to
employ an external non-volatile memory to store firmware or other information
such as vendor id, product id and device id (VID/PID/DID) permanently. The large
EEPROM ATMEL 24C64A is used to store the VID/PID/DID and the firmware for
Cypress chip. The MCU has a small non-volatile memory that contains Cypress
VID/PID/DID but that information cannot be changed for used in custom devices,
therefore there is a need to use an external EEPROM. This information is used later
when designing driver for the device.

12


CHAPTER III

SOFTWARE

III.1 Development Environment
In software development the “environment” is a term for the collection of
applications and compliers that are used in the development process of new
software. Firmware is another word for software, but is most often used if the
software is small and used in a small device such as an mp3-player or a digital
camera. In this project a few tools were used during firmware development. Keil
uVision2 combined with C51 C-complier was used to edit and compile the code for
firmware. To load the firmware to the [1] EZ-USB FX2LP, Cypress console was
used. The Cypress console is a windows application that is included with the
development kit and is used as a development platform. It can load firmware into a
connected Cypress device, transfer small amounts of data, reading endpoint
configuration and has many other features that can be used to test the firmware of a
device.

III.2 Firmware
III.2.1 EZ-USB Firmware FrameWorks

13


The Firmware FrameWorks simplifies and accelerates USB peripheral development
using the EZ-USB chip. The FrameWorks implements 8051 code for EZ-USB chip
initialization, USB standard device request handling, and USB suspend power
management services for the user. The user simply provides a USB descriptor table,
and code to implement the peripheral function to complete a fully compliant USB
device
FrameWorks Overview
The FrameWorks implements the basic functionality required of a USB compliant
peripheral device. By linking a minimal descriptor table, it is possible to build a
fully compliant Device Framework (USB spec Chapter 9) device without writing a
line of code. By linking code associated with the provided hooks, it is possible to
incrementally build a fully functional device.
The FrameWorks implements a simple co-operative tasking executive (See figure
below). At start-up, the FrameWorks first initializes all of its internal state variables.
It then calls the user initialization function TD_Init(). Upon return, the FrameWorks
initializes the USB interface to the unconfigured state and enables interrupts. The
firmware then ReNumerates and starts the cooperative task dispatcher. The task
dispatcher repeatedly performs the following tasks in the given order.
1. Calls user function TD_Poll().
2. Determines if a standard device request is pending. If so, it parses the
received command and responds accordingly. The FrameWorks automatically
handles the standard USB requests but allows the user to override the default
behavior for all requests.
3. Determines if the USB core has reported a USB suspend event. If so, it calls
the user function TD_Suspend().

EZ-USB USB interrupts are handled by the FrameWorks. It provides hooks for user
code notification of USB events.

14


Tài liệu bạn tìm kiếm đã sẵn sàng tải về

Tải bản đầy đủ ngay

×

×