Tải bản đầy đủ

CMOS VLSI Design - Lecture 4: Nonideal Transistor Theory pdf

Lecture 4:
Nonideal
Transistor
Theory
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 2
Outline
 Nonideal Transistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage

 Process and Environmental Variations
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 3
Ideal Transistor I-V
 Shockley long-channel transistor models
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
VV
V
I VV VVV
VV VV
β
β


<



= −− <





−>



CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 4
Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, V
DD
= 1.0 V
0
0.2
0.4
0.6
0.8 1
0
200
400
600
800
1000
1200
V
ds
I
ds
(µA)
V
gs
= 1.0
V
gs
= 1.0
V
gs
= 0.8
V
gs
= 0.6
V
gs
= 0.4
V
gs
= 0.8
V
gs
= 0.6
Channel length modulation:
Saturation current increases
with V
ds
I
on
= 747 mA @
V
gs
= V
ds
= V
DD
Simulated
Ideal
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with V
gs
Velocity saturation & Mobility degradation:
I
on
lower than ideal model predicts
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 5
ON and OFF Current
 I
on
= I
ds
@ V
gs
= V
ds
= V
DD
– Saturation
 I
off
= I
ds
@ V
gs
= 0, V
ds
= V
DD
– Cutoff
0
0.2 0.4 0.6
0.8 1
0
200
400
600
800
1000
V
ds
I
ds
(µA)
V
gs
= 1.0
V
gs
= 0.4
V
gs
= 0.8
V
gs
= 0.6
I
on
= 747 mA @
V
gs
= V
ds
= V
DD
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 6
Electric Fields Effects
 Vertical electric field: E
vert
= V
gs
/ t
ox
– Attracts carriers into channel
– Long channel: Q
channel
∝ E
vert
 Lateral electric field: E
lat
= V
ds
/ L
– Accelerates carriers from drain to source
– Long channel: v = µE
lat
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 7
Coffee Cart Analogy
 Tired student runs from VLSI lab to coffee cart
 Freshmen are pouring out of the physics lecture hall
 V
ds
is how long you have been up
– Your velocity = fatigue × mobility
 V
gs
is a wind blowing you against the glass (SiO
2
) wall
 At high V
gs
, you are buffeted against the wall
– Mobility degradation
 At high V
ds
, you scatter off freshmen, fall down, get up
– Velocity saturation
• Don’t confuse this with the saturation region
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 8
Mobility Degradation
 High E
vert
effectively reduces mobility
– Collisions with oxide interface
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 9
Velocity Saturation
 At high E
lat
, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches v
sat
• Electrons: 10
7
cm/s
• Holes: 8 x 10
6
cm/s
– Better model
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 10
Vel Sat I-V Effects
 Ideal transistor ON current increases with V
DD
2
 Velocity-saturated ON current increases with V
DD
 Real transistors are partially velocity saturated
– Approximate with α-power law model
– I
ds
∝ V
DD
α
– 1 < α < 2 determined empirically (≈ 1.3 for 65 nm)
( )
( )
2
2
ox
22
gs t
ds gs t
VV
W
I C VV
L
β
µ

= = −
( )
ox maxds gs t
I CWV V v= −
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 11
α-Power Model
0 cutoff
linear
saturation
gs t
ds
ds dsat ds dsat
dsat
dsat ds dsat
VV
V
I I VV
V
I VV

<


= <



>

( )
( )
/2
2
dsat c gs t
dsat v gs t
I PVV
V PV V
α
α
β
= −
= −
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 12
Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion L
d
region grows with reverse bias
– L
eff
= L – L
d
 Shorter L
eff
gives more current
– I
ds
increases with V
ds
– Even in saturation
n
+
p
GateSource Drain
bulk Si
n
+
V
DD
GND
V
DD
GND
L
L
eff
Depletion Region
Width: L
d
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 13
Chan Length Mod I-V
 λ = channel length modulation coefficient
– not feature size
– Empirically fit to I-V characteristics
( )
( )
2
1
2
ds gs t ds
I VV V
β
λ
= −+
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 14
Threshold Voltage Effects
 V
t
is V
gs
for which the channel starts to invert
 Ideal models assumed V
t
is constant
 Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 15
Body Effect
 Body is a fourth transistor terminal
 V
sb
affects the charge required to invert the channel

Increasing V
s
or decreasing V
b
increases V
t
 φ
s
= surface potential at threshold
– Depends on doping level N
A
– And intrinsic carrier concentration n
i
 γ = body effect coefficient
( )
0t t s sb s
VV V
γφ φ
=+ +−
2 ln
A
sT
i
N
v
n
φ
=
si
ox
si
ox ox
2q
2q
A
A
N
t
N
C
ε
γε
ε
= =
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 16
Body Effect Cont.
 For small source-to-body voltage, treat as linear
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 17
DIBL
 Electric field from drain affects channel
 More pronounced in small transistors where the
drain is closer to the channel
 Drain-Induced Barrier Lowering
– Drain voltage also affect V
t
 High drain voltage causes current to increase.
ttdsVVV
η
t t ds
VV V
η

= −
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 18
Short Channel Effect
 In small transistors, source/drain depletion regions
extend into the channel
– Impacts the amount of charge required to invert
the channel
– And thus makes V
t
a function of channel length
 Short channel effect: V
t
increases with L
– Some processes exhibit a reverse short channel
effect in which V
t
decreases with L
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 19
Leakage
 What about current in cutoff?
 Simulated results
 What differs?
– Current doesn’t
go to 0 in cutoff
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 20
Leakage Sources
 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
– Dominant source in contemporary transistors
 Gate leakage
– Tunneling through ultrathin gate dielectric
 Junction leakage
– Reverse-biased PN junction diode current
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 21
Subthreshold Leakage
 Subthreshold leakage exponential with V
gs
 n is process dependent
– typically 1.3-1.7

Rewrite relative to I
off
on log scale
 S ≈ 100 mV/decade @ room temperature
0
0
e 1e
gs t ds sb
ds
TT
V V V kV
V
nv v
ds ds
II
γ
η
−+ −


= −



CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 22
Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to t
ox
and V
DD
– A and B are tech constants
– Greater for electrons
• So nMOS gates leak more
 Negligible for older processes (t
ox
> 20 Å)
 Critically important at 65 nm and below (t
ox
≈ 10.5 Å)
From [Song01]
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 23
Junction Leakage
 Reverse-biased p-n junctions have some leakage
– Ordinary diode leakage
– Band-to-band tunneling (BTBT)
– Gate-induced drain leakage (GIDL)
n well
n+n+ n+
p+p+p+
p substrate
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 24
Diode Leakage
 Reverse-biased p-n junctions have some leakage
 At any significant negative diode voltage, I
D
= -I
s
 I
s
depends on doping levels
– And area and perimeter of diffusion regions
– Typically < 1 fA/µm
2
(negligible)
e1
D
T
V
v
DS
II

= −



CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 25
Band-to-Band Tunneling
 Tunneling across heavily doped p-n junctions
– Especially sidewall between drain & channel
when halo doping is used to increase V
t
 Increases junction leakage to significant levels
– X
j
: sidewall junction depth
– E
g
: bandgap voltage
– A, B: tech constants

Tài liệu bạn tìm kiếm đã sẵn sàng tải về

Tải bản đầy đủ ngay

×